There are known advantages to having a memory array contained within a well which is pumped to a voltage which is greater than the voltage of the positive power supply in the case of an N well and less than the voltage of the negative power supply voltage in the case of a P well. In present technology, especially MOS, the common positive power supply is nominally at 5 volts and the negative power supply is at ground. During power-up, however, there is a potential problem with the pumped-well approach. Because the array well is pumped, it is not directly connected to a power supply terminal. There is a lag time for the array well to reach its pumped voltage. During this lag time, the power supply voltage may exceed the array well voltage. If this happens, a PN junction may be forward biased and induce latch-up.
In the case of a dynamic random access memory (DRAM) that has P channel transistors as the transfer devices, the array will be in an N-type well which is biased to a voltage in excess of the positive power supply, for example, one and a half times the positive power supply. In such a case the P channel transfer devices have source/drains of P-type material which are connected to bit lines. If power-up is treated the same as normal, at least some of the bit lines are almost certainly going to be coupled to the positive supply. In such case, the source/drain of a transfer device may exceed the voltage of the array well by an amount sufficient to cause current to flow therebetween and induce latch-up.
One solution to this problem is disclosed in U.S. Pat. No. 4,670,861, Shu et al. The solution described therein was to force the bit lines to one half the positive power supply (Vcc) during power-up. A power-up circuit was used to provide information as to the relationship of the array voltage to Vcc. When the array-well voltage reached one P channel threshold voltage above Vcc, then the power-up circuit would release control. During the precharge cycle, the bit lines were normally brought to 1/2 Vcc so the power-up circuit affected the 1/2 Vcc bit line condition by forcing the memory into the same condition as is present during the precharge cycle during power-up.
This solution was available because a 1/2 Vcc source with relatively high current capacity was already present. For the type of DRAM in which the bit lines are equalized to obtain the 1/2 Vcc voltage, there is no such 1/2 Vcc voltage source available. Additionally, even limiting the bit lines to 1/2 Vcc does not necessarily ensure that the bit line voltage will not exceed the array-well voltage. The rise time of the bit lines could still be faster than that of the array well. Consequently, the solution thus requires a separately generated voltage which may not already be available and it may not be sufficient for controlling the rise rate of the bit lines with respect to the rate for the array well.